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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a lc 2 mos 12-bit dacports ad7245a/ad7248a one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features 12-bit cmos dac with output amplifier and reference improved ad7245/ad7248: 12 v to 15 v operation 6 1/2 lsb linearity grade faster interfaceC30 ns typ data setup time extended plastic temperature range (C40 8 c to +85 8 c) single or dual supply operation low powerC65 mw typ in single supply parallel loading structure: ad7245a (8+4) loading structure: ad7248a general description the ad7245a/ad7248a is an enhanced version of the industry standard ad7245/ad7248. improvements include operation from 12 v to 15 v supplies, a 1/2 lsb linearity grade, faster interface times and better full scale and reference variations with v dd . additional features include extended temperature range operation for commercial and industrial grades. the ad7245a/ad7248a is a complete, 12-bit, voltage output, digital-to-analog converter with output amplifier and zener volt- age reference on a monolithic cmos chip. no external user trims are required to achieve full specified performance. both parts are microprocessor compatible, with high speed data latches and double-buffered interface logic. the ad7245a ac- cepts 12-bit parallel data which is loaded into the input latch on the rising edge of cs or wr . the ad7248a has an 8-bit wide data bus with data loaded to the input latch in two write opera- tions. for both parts, an asynchronous ldac signal transfers data from the input latch to the dac latch and updates the ana- log output. the ad7245a also has a clr signal on the dac latch which allows features such as power-on reset to be implemented. the on-chip 5 v buried zener diode provides a low noise, tem- perature compensated reference for the dac. for single supply operation, two output ranges of 0 v to +5 v and 0 v to +10 v are available, while these two ranges plus an additional 5 v range are available with dual supplies. the output amplifiers are capable of developing +10 v across a 2 k w load to gnd. the ad7245a/ad7248a is fabricated in linear compatible cmos (lc 2 mos), an advanced, mixed technology process that combines precision bipolar circuits with low power cmos logic. the ad7245a is available in a small, 0.3" wide, 24-pin dip and dacport is a registered trademark of analog devices, inc. ad7245a functional block diagram ad7248a functional block diagram soic and in 28-terminal surface mount packages. the ad7248a is packaged in a small, 0.3" wide, 20-pin dip and soic and in 20-terminal surface mount packages. product highlights 1. the ad7245a/ad7248a is a 12-bit dacport ? on a single chip. this single chip design and small package size offer considerable space saving and increased reliability over multichip designs. 2. the improved interface times on the part allows easy, direct interfacing to most modern microprocessors. 3. the ad7245a/ad7248a features a wide power supply range allowing operation from 12 v supplies.
a 2 b 2 t 2 parameter version version version units test conditions/comments static performance resolution 12 12 12 bits relative accuracy @ +25 c 3 3/4 1/2 1/2 lsb max t min to t max 1 3/4 3/4 lsb max t min to t max 1/2 lsb max v dd = 15 v 5% differential nonlinearity 3 1 1 1 lsb max guaranteed monotonic unipolar offset error @ +25 c 3 3 3 3 lsb max v ss = 0 v or C12 v to C15 v 4 t min to t max 5 5 5 lsb max typical tempco is 3 ppm of fsr 5 / c. bipolar zero error @ +25 c 3 3 2 2 lsb max r ofs connected to ref out; v ss = C12 v to C15 v 4 t min to t max 5 4 4 lsb max typical tempco is 3 ppm of fsr 5 / c. dac gain error 3, 6 2 2 2 lsb max full-scale output voltage error 7 @ +25 c 0.2 0.2 0.2 % of fsr max v dd = +15 v d full scale/ d v dd 0.06 0.06 0.06 % of fsr/v max v dd = +12 v to +15 v 4 d full scale/ d v ss 0.01 0.01 0.01 % of fsr/v max v ss = C12 v to C15 v 4 full-scale temperature coefficient 8 30 30 40 ppm of fsr/ c max v dd = +15 v reference output ref out @ +25 c 4.99/5.01 4.99/5.01 4.99/5.01 v min/v max v dd = +15 v d ref out/ d v dd 2 2 2 mv/v max v dd = +12 v to +15 v 4 reference temperature coefficient 25 25 35 ppm/ c typ reference load change ( d ref out vs. d i) C1 C1 C1 mv max referenee load current change (0C100 m a) digital inputs input high voltage, v inh 2.4 2.4 2.4 v min input low voltage, v inl 0.8 0.8 0.8 v max input current, i in 10 10 10 m a max v in = 0 v to v dd input capacitance 9 8 8 8 pf max analog outputs output range resistors 15/30 15/30 15/30 k w min/k w max output voltage ranges 10 +5, +10 +5, +10 +5, +10 v v ss = 0 v; pin strappable output voltage ranges 10 +5, +10, +5, +10, +5, +10, v ss = C12 v to C15 v; 4 pin strappable 5 5 5v dc output impedance 0.5 0.5 0.5 w typ ac characteristics 9 voltage output settling time settling time to within 1/2 lsb of final value positive full-scale change 7 7 10 m s max dac latch all 0s to all 1s negative full-scale change 7 7 10 m s max dac latch all 1s to all 0s; v ss = C12 v to C15 v 4 output voltage slew rate 2 2 1.5 v/ m s min digital feedthrough 3 10 10 10 nv-s typ digital-to-analog glitch impulse 30 30 30 nv-s typ power requirements v dd +10.8/ +11.4/ +11.4/ v min/ for specified performance unless otherwise stated +16.5 +15.75 +15.75 v max v ss C10.8/ C11.4/ C11.4/ v min/ for specified performance unless otherwise stated C16.5 C15.75 C15.75 v max i dd @ +25 c 9 9 9 ma max output unloaded; typically 5 ma t mln to t max 10 10 12 ma max output unloaded i ss (dual supplies) 3 3 5 ma max output unloaded; typically 2 ma notes 1 power supply tolerance is 10% for a version and 5% for b and t versions. 2 temperature ranges are as follows: a/b versions; C40 c to +85 c; t version; C55 c to +125 c. 3 see terminology. 4 with appropriate power supply tolerances. 5 fsr means full-scale range and is 5 v for the 0 v to +5 v output range and 10 v for both the 0 v to +10 v and 5 v output ranges. 6 this error is calculated with respect to the reference voltage and is measured after the offset error has been allowed for. 7 this error is calculated with respect to an ideal 4.9988 v on rhe 0 v to +5 v and 5 v ranges; it is calculated with respect to an ideal 9.9976 v on the 0 v to +10 v range. it includes the effects of internal voltage reference, gain and offset errors. 8 full-scale tc = d fs/ d t, where d fs is the full-scale change from t a = +25 c to t min or t max . 9 sample tested at +25 c to ensure compliance. 10 0 v to +10 v output range is available only when v dd 3 +14.25 v. specifications subject to change without notice. ad7245a/ad7248aCspecifications rev. a C2C (v dd = +12 v to +15 v, 1 v ss = o v or C12 v to C15 v, 1 agnd = dgnd = o v, r l = 2 k v , c l = 1oo pf. all specifications t min to t max unless otherwise noted.)
ad7245a/ad7248a rev. a C3C switching characteristics 1 (v dd = +12 v to +15 v; 2 v ss = o v or C12 v to C15 v; 2 see figures 5 and 7.) parameter a, b versions t version units conditions t 1 @ +25 c 55 55 ns typ chip select pulse width t min to t max 80 100 ns min t 2 @ +25 c 40 40 ns typ write pulse width t min to t max 80 100 ns min t 3 @ +25 c 0 0 ns min chip select to write setup time t min to t max 0 0 ns min t 4 @ +25 c 0 0 ns min chip select to write hold time t min to t max 0 0 ns min t 5 @ +25 c 40 40 ns typ data valid to write setup time t min to t max 80 80 ns min t 6 @ +25 c 10 10 ns min data valid to write hold time t min to t max 10 10 ns min t 7 @ +25 c 40 40 ns typ load dac pulse width t min to t max 80 100 ns min t 8 (ad7245a only) @ +25 c 40 40 ns typ clear pulse width t min to t max 80 100 ns min notes 1 sample tested at +25 c to ensure compliance. 2 power supply tolerance is 10% for a version and 5% for b and t versions. absolute maximum ratings 1 v dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . .C0.3 v to +17 v v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . .C0.3 v to +17 v v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . .C0.3 v to +34 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, v dd digital input voltage to dgnd . . . . . . . . C0.3 v, v dd +0.3 v v out to agnd 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss , v dd v out to v ss 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v, +24 v v out to v dd 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C32 v, 0 v ref out 2 to agnd . . . . . . . . . . . . . . . . . . . . . . . . 0 v, v dd power dissipation (any package) to +75 c . . . . . . . . 450 mw derates above +75 c by . . . . . . . . . . . . . . . . . . . . 6 mw/ c operating temperature commercial (a, b versions) . . . . . . . . . . . C40 c to +85 c extended (s version) . . . . . . . . . . . . . . . C55 c to +125 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause per- manent damage to the device. this is a stress rating only and functional opera- tion of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 the output may be shorted to voltages in this range provided the power dissipa- tion of the package is not exceeded. v out short circuit current is typically 80 ma. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7245a/ad7248a features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of function- ality.
ad7245a/ad7248a rev. a C4C dac gain error dac gain error is a measure of the output error between an ideal dac and the actual device output with all 1s loaded after offset error has been allowed for. it is, therefore defined as: measured valueoffsetideal value where the ideal value is calculated relative to the actual refer- ence value. unipolar offset error unipolar offset error is a combination of the offset errors of the voltage mode dac and the output amplifier and is measured when the part is configured for unipolar outputs. it is present for all codes and is measured with all 0s in the dac register. bipolar zero offset error bipolar zero offset error is measured when the part is config- ured for bipolar output and is a combination of errors from the dac and output amplifier. it is present for all codes and is measured with a code of 2048 (decimal) in the dac register. single supply linearity and gain error the output amplifier of the ad7245a/ad7248a can have a true negative offset even when the part is operated from a single positive power supply. however, because the lower supply rail to the part is 0 v, the output voltage cannot actually go nega- tive. instead the output voltage sits on the lower rail and this re- sults in the transfer function shown. this is an offset effect and the transfer function would have followed the dotted line if the output voltage could have gone negative. normally, linearity is measured after offset and full scale have been adjusted or al- lowed for. on the ad7245a/ad7248a the negative offset is al- lowed for by calculating the linearity from the code which the amplifier comes off the lower rail. this code is given by the negative offset specification. for example, the single supply lin- earity specification applies between code 3 and code 4095 for the 25 c specification and between code 5 and code 4095 over the t min to t max temperature range. since gain error is also measured after offset has been allowed for, it is calculated between the same codes as the linearity error. bipolar linearity and gain er- ror are measured between code 0 and code 4095. output voltage negative offset dac code 0v { terminology relative accuracy relative accuracy, or end-point nonlinearity, is a measure of the actual deviation from a straight line passing through the end- points of the dac transfer function. it is measured after allow- ing for zero and full scale and is normally expressed in lsbs or as a percentage of full-scale reading. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb max over the operating temperature range ensures monotonicity. digital feedthrough digital feedthrough is the glitch impulse injected from the digi- tal inputs to the analog output when the inputs change state. it is measured with ldac high and is specified in nv-s. ad7245a ordering guide temperature relative package model l range accuracy option 2 ad7245aan C40 c to +85 c 3/4 lsb n-24 ad7245abn C40 c to +85 c 1/2 lsb n-24 ad7245aaq C40 c to +85 c 3/4 lsb q-24 ad7245atq 3 C55 c to +125 c 3/4 lsb q-24 ad7245aap C40 c to +85 c 3/4 lsb p-28a ad7245aar C40 c to +85 c 3/4 lsb r-24 ad7245abr C40 c to +85 c 1/2 lsb r-24 ad7245ate 3 C55 c to +125 c 3/4 lsb e-28a notes 1 to order mil-std-883, class b. processed parts, add /883b to part number. contact our local sales office for military data sheet and availability. 2 e = leadless ceramic chip carrier; n = plastic dip; p = plastic leaded chip carrier; q = cerdip; r = soic. 3 this grade will be available to /883b processing only. ad7248a ordering guide temperature relative package model l range accuracy option 2 ad7248aan C40 c to +85 c 3/4 lsb n-20 ad7248abn C40 c to +85 c 1/2 lsb n-20 AD7248AAQ C40 c to +85 c 3/4 lsb q-20 ad7248atq 3 C55 c to +125 c 3/4 lsb q-20 ad7248aap C40 c to +85 c 3/4 lsb p-20a ad7248aar C40 c to +85 c 3/4 lsb r-20 ad7248abr C40 c to +85 c 1/2 lsb r-20 notes 1 to order mil-std-883, class b, processed parts, add /883b to part number. contact our local sales office for military data sheet and availability. 2 n = plastic dip; p = plastic leaded chip carrier; q = cerdip; r = soic. 3 this grade will be available to /883b processing only.
ad7245a/ad7248a rev. a C5C ad7248a pin function description (dip pin numbers) pin mnemonic description lv ss negative supply voltage (0 v for single supply operation). 2r ofs bipolar offset resistor. this provides access to the on-chip application resistors and allows different output voltage ranges. 3 ref out reference output. the on-chip reference is provided at this pin and is used when configuring the part for bipolar outputs. 4 agnd analog ground. 5 db11 data bit 11. most significant bit (msb). 6-11 db10-db5 data bit 10 to data bit 5. 12 dgnd digital ground. 13-16 db4-db1 data bit 4 to data bit 1. 17 db0 data bit 0. least significant bit (lsb). 18 cs chip select input (active low). the de- vice is selected when this input is active. pin mnemonic description 19 wr write input (active low). this is used in conjunction with cs to write data into the input latch of the ad7245a. 20 ldac load dac input (active low). this is an asynchronous input which when active transfers data from the input latch to the dac latch. 21 clr clear input (active low). when this in- put is active the contents of the dac latch are reset to all 0s. 22 v dd positive supply voltage. 23 r fb feedback resistor. this allows access to the amplifiers feedback loop. 24 v out output voltage. three different output voltage ranges can be chosen: 0 v to +5 v, 0 v to +10 v or C5 v to +5 v. plcc ad7245a pin configurations dip and soic lccc
ad7245a/ad7248a rev. a C6C ad7248a pin function description (any package) pin mnemonic description l v ss negative supply voltage (0 v for single supply operation). 2 r ofs bipolar offset resistor. this provides access to the on-chip application resistors and allows different output voltage ranges. 3 ref out reference output. the on-chip reference is provided at this pin and is used when configuring the part for bipolar outputs. 4 agnd analog ground. 5 db7 data bit 7. 6 db6 data bit 6. 7 db5 data bit 5. 8 db4 data bit 4. 9 db3 data bit 3. 10 dgnd digital ground. 11 db2 data bit 2/data bit 10. 12 db1 data bit 1/data bit 9. 13 db0 data bit 0 (lsb)/data bit 8. pin mnemonic description 14 csmsb chip select input for ms nibble. (active low). this selects the upper 4 bits of the input latch. input data is right justified. 15 cslsb chip select input for ls byte. (active low). this selects the lower 8 bits of the input latch. 16 wr write input. this is used in conjunction with csmsb and cslsb to load data into the input latch of the ad7248a. 17 ldac load dac input (active low). this is an asynchronous input which when active transfers data from the input latch to the dac latch. 18 v dd positive supply voltage. 19 r fb feedback resistor. this allows access to the amplifiers feedback loop. 20 v out output voltage. three different output voltage ranges can be chosen: 0 v to +5 v, 0 v to +10 v or C5 v to +5 v. ad7248a pin configurations lccc plcc dip and soic
rev. a C7C typical performanceCad7245a/ad7248a power supply current vs. temperature noise spectral density vs. frequency positive-going settling time (v dd = +15 v, v ss = C15 v) reference voltage vs. temperature power supply rejection ration vs. frequency negative going settling time (v dd = +15 v, v ss = C15 v)
ad7245a/ad7248a rev. a C8C circuit information d/a section the ad7245a/ad7248a contains a 12-bit voltage mode digi- tal-to-analog converter. the output voltage from the converter has the same positive polarity as the reference voltage allowing single supply operation. the reference voltage for the dac is provided by an on-chip buried zener diode. the dac consists of a highly stable, thin-film, rC2r ladder and twelve high-speed nmos single-pole, double-throw switches. the simplified circuit diagram for this dac is shown in figure 1. figure 1. d/a simplified circuit diagram the input impedance of the dac is code dependent and can vary from 8 k w to infinity. the input capacitance also varies with code, typically from 50 pf to 200 pf. op amp section the output of the voltage mode d/a converter is buffered by a noninverting cmos amplifier. the user has access to two gain setting resistors which can be connected to allow different out- put voltage ranges (discussed later). the buffer amplifier is ca- pable of developing up to 10 v across a 2 k w load to gnd. the output amplifier can be operated from a single positive power supply by tying v ss = agnd = 0 v. the amplifier can also be operated from dual supplies to allow a bipolar output range of C5 v to +5 v. the advantages of having dual supplies for the unipolar output ranges are faster settling time to voltages near 0 v, full sink capability of 2.5 ma maintained over the en- tire output range and elimination of the effects of negative offset on the transfer characteristic (outlined previously). figure 2 shows the sink capability of the amplifier for single supply operation. figure 2. typical single supply sink current vs. output voltage the small signal (200 mv p-p) bandwidth of the output buffer amplifier is typically 1 mhz. the output noise from the ampli- fier is low with a figure of 25 nv/ ? hz at a frequency of 1 khz. the broadband noise from the amplifier has a typical peak-to- peak figure of 150 m v for a 1 mhz output bandwidth. there is no significant difference in the output noise between single and dual supply operation. voltage reference the ad7245a/ad7248a contains an internal low noise buried zener diode reference which is trimmed for absolute accuracy and temperature coefficient. the reference is internally con- nected to the dac. since the dac has a variable input imped- ance at its reference input the zener diode reference is buffered. this buffered reference is available to the user to drive the cir- cuitry required for bipolar output ranges. it can be used as a ref- erence for other parts in the system provided it is externally buffered. the reference will give long-term stability comparable with the best discrete zener reference diodes. the performance of the ad7245a/ad7248a is specified with internal reference, and all the testing and trimming is done with this reference. the reference should be decoupled at the ref out pin and recom- mended decoupling components are 10 m f and 0.1 m f capaci- tors in series with a 10 w resistor. a simplified schematic of the reference circuitry is shown in figure 3. figure 3. internal reference digital section the ad7245a/ad7248a digital inputs are compatible with ei- ther ttl or 5 v cmos levels. all data inputs are static pro- tected mos gates with typical input currents of less than 1 na. the control inputs sink higher currents (150 m a max) as a result of the fast digital interfacing. internal input protection of all logic inputs is achieved by on-chip distributed diodes. the ad7245a/ad7248a features a very low digital feedthrough figure of 10 nv-s in a 5 v output range. this is due to the volt- age mode configuration of the dac. most of the impulse is ac- tually as a result of feedthrough across the package. interface logic informationad7245a table i shows the truth table for ad7245a operation. the part contains two 12-bit latches, an input latch and a dac latch. cs and wr control the loading of the input latch while ldac con- trols the transfer of information from the input latch to the dac latch. all control signals are level triggered; and therefore, either or both latches may be made transparent, the input latch by keeping cs and wr low, the dac latch by keeping ldac low. input data is latched on the rising edge of wr .
ad7245a/ad7248a rev. a C9C the data held in the dac latch determines the analog output of the converter. data is latched into the dac latch on the rising edge of ldac . this ldac signal is an asynchronous signal and is independent of wr . this is useful in many applications. however, in systems where the asynchronous ldac can occur during a write cycle (or vice versa) care must be taken to ensure that incorrect data is not latched through to the output. for ex- ample, if ldac goes low while wr is low, then the ldac signal must stay low for t 7 or longer after wr goes high to ensure correct data is latched through to the output. table i. ad7245a truth table clr ldac wr cs function h l l l both latches are transparent h h h x both latches are latched h h x h both latches are latched h h l l input latches transparent hh g l input latches latched h l h h dac latches transparent h g h h dac latches latched l x x x dac latches loaded with all 0s g h h h dac latches latched with all 0s and output remains at 0 v or C5 v g l l l both latches are transparent and output follows input data h = high state l = low state x = dont care the contents of the dac latch are reset to all 0s by a low level on the clr line. with both latches transparent, the clr line functions like a zero override with the output brought to 0 v in the unipolar mode and C5 v in the bipolar mode for the dura- tion of the clr pulse. if both latches are latched, a low pulse on the clr input latches all 0s into the dac latch and the output remains at 0 v (or C5 v) after the clr line has re- turned high. the clr line can be used to ensure powerup to 0 v on the ad7245a output in unipolar operation and is also useful, when used as a zero override, in system calibration cycles. figure 4 shows the input control logic for the ad7245a and the write cycle timing for the part is shown in figure 5. figure 4. ad7245a input control logic figure 5. ad7245a write cycle timing diagram interface logic informationad7248a the input loading structure on the ad7248a is configured for interfacing to microprocessors with an 8-bit wide data bus. the part contains two 12-bit latchesan input latch and a dac latch. only the data held in the dac latch determines the ana- log output from the converter. the truth table for ad7248a operation is shown in table ii, while the input control logic dia- gram is shown in figure 6. figure 6. ad7248a input control logic csmsb , cslsb and wr control the loading of data from the external data bus to the input latch. the eight data inputs on the ad7248a accept right justified data. this data is loaded to the input latch in two separate write operations. cslsb and wr control the loading of the lower 8-bits into the 12-bit wide latch. the loading of the upper 4-bit nibble is controlled by csmsb and wr . all control inputs are level triggered, and in- put data for either the lower byte or upper 4-bit nibble is latched into the input latches on the rising edge of wr (or either csmsb or cslsb ). the order in which the data is loaded to the input latch (i.e., lower byte or upper 4-bit nibble first) is not important. the ldac input controls the transfer of 12-bit data from the input latch to the dac latch. this ldac signal is also level triggered, and data is latched into the dac latch on the rising edge of ldac . the ldac input is asynchronous and indepen- dent of wr . this is useful in many applications especially in
ad7245a/ad7248a rev. a C10C the simultaneous updating of multiple ad7248a outputs. how- ever, in systems where the asynchronous ldac can occur dur- ing a write cycle (or vice versa) care must be taken to ensure that incorrect data is not latched through to the output. in other words, if ldac goes low while wr and either cs input are low (or wr and either cs go low while ldac is low), then the ldac signal must stay low for t 7 or longer after wr returns high to ensure correct data is latched through to the output. the write cycle timing diagram for the ad7248a is shown in figure 7. figure 7. ad7248a write cycle timing diagram an alternate scheme for writing data to the ad7248a is to tie the csmsb and ldac inputs together. in this case exercising cslsb and wr latches the lower 8 bits into the input latch. the second write, which exercises csmsb , wr and ldac loads the upper 4-bit nibble to the input latch and at the same time transfers the 12-bit data to the dac latch. this automatic transfer mode updates the output of the ad7248a in two write operations. this scheme works equally well for cslsb and ldac tied together provided the upper 4-bit nibble is loaded to the input latch followed by a write to the lower 8 bits of the in- put latch. table ii. ad7248a truth table cslsb csmsb wr ldac function l h l h i.oad ls byte into input latch lh g h latches ls byte into input latch g h l h latches ls byte into input latch h l l h loads ms nibble into input latch hl g h latches ms nibble into input latch h g l h latches ms nibble into input latch h h h l loads input latch into dac latch hh h g latches input latch into dac latch h l l l loads ms nibble into input latch and loads input latch into dac latch h h h h no data transfer operation h = high state l = low state applying the ad7245a/ad7248a the internal scaling resistors provided on the ad7245a/ ad7248a allow several output voltage ranges. the part can produce unipolar output ranges of 0 v to +5 v or 0 v to +10 v and a bipolar output range of C5 v to +5 v. connections for the various ranges are outlined below. unipolar (0 v to +10 v) configuration the first of the configurations provides an output voltage range of 0 v to +10 v. this is achieved by connecting the bipolar off- set resistor, r ofs , to agnd and connecting r fb to v out . in this configuration the ad7245a/ad7248a can be operated single supply (v ss = 0 v = agnd). if dual supply performance is required, a v ss of C12 v to C15 v should be applied. figure 8 shows the connection diagram for unipolar operation while the table for output voltage versus the digital code in the dac latch is shown in table iii. figure 8. unipolar (0 to +10 v) configuration table iii. unipolar code table (0 v to +10 v range) dac latch contents msb lsb analog output, v out 1 1 1 1 1 1 1 1 1 1 1 1 +2 v ref 3 4095 4096 ? ? ? ? 1 0 0 0 0 0 0 0 0 0 0 1 +2 v ref 3 2049 4096 ? ? ? ? 1 0 0 0 0 0 0 0 0 0 0 0 +2 v ref 3 2048 4096 ? ? ? ? =+ v ref 0 1 1 1 1 1 1 1 1 1 1 1 +2 v ref 3 2047 4096 ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 1 +2 v ref 3 1 4096 ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 v note: 1 lsb = 2 3 v ref (2 C12 ) = v ref 1 2048 ? ? ? ? unipolar (0 v to +5 v) configuration the 0 v to +5 v output voltage range is achieved by tying r ofs , r fb and v out together. for this output range the ad7245a/ ad7248a can be operated single supply (v ss = 0 v) or dual supply. the table for output voltage versus digital code is as in table iii, with 2 ? v ref replaced by v ref . note that for this range 1 lsb = v ref (2 C12 ) = v ref 3 1 4096 ? ? ? ? .
ad7245a/ad7248a rev. a C11C bipolar configuration the bipolar configuration for the ad7245a/ad7248a, which gives an output voltage range from C5 v to +5 v, is achieved by connecting the r ofs input to ref out and connecting r fb and v out . the ad7245a/ad7248a must be operated from dual supplies to achieve this output voltage range. the code table for bipolar operation is shown in table iv. table iv. bipolar code table dac latch contents msb lsb analog output, v out 1 1 1 1 1 1 1 1 1 1 1 1 + v ref 2047 2048 ? ? ? ? 1 0 0 0 0 0 0 0 0 0 0 1 + v ref 1 2048 ? ? ? ? 1 0 0 0 0 0 0 0 0 0 0 0 0 v 0 1 1 1 1 1 1 1 1 1 1 1 C v ref 1 2048 ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 1 C v ref 2047 2048 ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 C v ref 2048 2048 ? ? ? ? = v ref note: 1 lsb = 2 v ref (2 C11 ) = v ref 1 2048 ? ? ? ? agnd bias the ad7245a/ad7248a agnd pin can be biased above sys- tem gnd (ad7245a/ad7248a dgnd) to provide an offset zero analog output voltage level. with unity gain on the am- plifier (r ofs = v out = r fb ) the output voltage, v out is ex- pressed as: v out = v bias + d 3 v ref where d is a fractional representation of the digital word in the dac latch and v bias is the voltage applied to the ad7245a/ ad7248a agnd pin. because the current flowing out of the agnd pin varies with digital code, the agnd pin should be driven from a low imped- ance source. a circuit configuration is outlined for agnd bias in figure 9 using the ad589, a +1.23 v bandgap reference. if a gain of 2 is used on the buffer amplifier the output voltage, v out is expressed as v out = 2(v bias + d 3 v ref ) in this case care must be taken to ensure that the maximum out- put voltage is not greater than v dd C3 v. the v dd Cv out over- head must be greater than 3 v to ensure correct operation of the part. note that v dd and v ss for the ad7245a/ad7248a must be referenced to dgnd (system gnd). the entire circuit can be operated in single supply with the v ss pin of the ad7245a/ ad7248a connected to system gnd. figure 9. agnd bias circuit programmable current sink figure 10 shows how the ad7245a/ad7248a can be config- ured with a power mosfet transistor, the vn0300m, to pro- vide a programmable current sink from v dd or v source . the vn0300m is placed in the feedback of the ad7245a/ ad7248a amplifier. the entire circuit can be operated in single supply by tying the v ss of the ad7245a/ad7248a to agnd. the sink current, i sink , can be expressed as: i sink = d v ref r 1 figure 10. programmable current sink using the vn0300m, the voltage drop across the load can typi- cally be as large as v source C6 v) with v out of the dac at +5 v. therefore, for a current of 50 ma flowing in the r1 (with all 1s in the dac register) the maximum load is 200 w with v source = +15 v. the vn0300m can actually handle currents up to 500 ma and still function correctly in the circuit, but in practice the circuit must be used with larger values of v source otherwise it requires a very small load. since the tolerance value on the reference voltage of the ad7245a/ad7248a is 0.2%, then the absolute value of i sink can vary by 0.2% from device to device for a fixed value of r1. because the input bias current of the ad7245a/ad7248as op amp is only of the order of picoamps, its effect on the sink cur- rent is negligible. tying the r ofs input to r fb input reduces this effect even further and prevents noise pickup which could occur if the r ofs pin was left unconnected.
ad7245a/ad7248a rev. a C12C the circuit of figure 10 can be modified to provide a program- mable current source to agnd or Cv sink (for Cv sink , dual sup- plies are required on the ad7245a/ad7248a). the ad7245a/ ad7248a is configured as before. the current through r1 is mirrored with a current mirror circuit to provide the program- mable source current (see cmos dac application guide, publication no. g872-30-10/84, for suitable current mirror cir- cuit). as before the absolute value of the source current will be affected by the 0.2% tolerance on v ref . in this case the per- formance of the current mirror will also affect the value of the source current. function generator with programmable frequency figure 11 shows how the ad7245a/ad7248a with the ad537, voltage-to-frequency converter and the ad639, trigonometric function generator to provide a complete function generator with programmable frequency. the circuit provides square wave, triwave and sine wave outputs, each output of 10 v amplitude. the ad7245a/ad7248a provides a programmable voltage to the ad537 input. since both the ad7245a/ad7248a and ad537 are guaranteed monotonic, the output frequency will al- ways increase with increasing digital code. the ad537 provides a square wave output which is conditioned for 10 v by ampli- fier a1. the ad537 also provides a differential triwave output. this is conditioned by amplifiers a2 and a3 to provide the 1.8 v triwave required at the input of the ad639. the triwave is further scaled by amplifier a4 to provide a 10 v output. adjusting the triwave applied to the ad639 adjust the distortion performance of the sine wave output, (+10 v in configuration shown). amplitude, offset and symmetry of the triwave can af- fect the distortion. by adjusting these, via vr1 and vr2, an output sine wave with harmonic distortion of better than C50 db can be achieved at low and intermediate frequencies. using the capacitor value shown in figure 11 for c f (i.e., 680 pf) the output frequency range is 0 to 100 khz over the digital input code range. the step size for frequency increments is 25 hz. the accuracy of the output frequency is limited to 8 or 9 bits by the ad537, but is guaranteed monotonic to 12 bits. microprocessor interfacingad7245 ad7245a8086a interface figure 12 shows the 8086 16-bit processor interfacing to the ad7245a. in the setup shown the double buffering feature of the dac is not used and the ldac input is tied low. ad0C ad11 of the 16-bit data bus are connected to the ad7245a data bus (db0-db11). the 12-bit word is written to the ad7245a in one mov instruction and the analog output re- sponds immediately. in this example the dac address is d000. a software routine for figure 12 is given in table v. figure 12. ad7245a to 8086 interface figure 11. programmable function generator table v. sample program for loading ad7245a from 8086 assume ds: dacload, cs: dacload dacload segment at 000 00 8cc9 mov cs, : define data segment cs register 02 8ed9 mov ds, : equal to code cx segment register 04 bf00d0 0mov di, : load di with d000 #d000 07 c705 mov mem, : dac loaded with wxyz yzwx #yzwx 0b ea00 00 : control is returned to 0e 00 ff the monitor program
ad7245a/ad7248a rev. a C13C in a multiple dac system the double buffering of the ad7245a allows the user to simultaneously update all dacs. in figure 13, a 12-bit word is loaded to the input latches of each of the dacs in sequence. then, with one instruction to the appropri- ate address, cs4 (i.e., ldac ) is brought low, updating all the dacs simultaneously. figure 13. ad7245a to 8086 multiple dac interface ad7245amc68000 interface interfacing between the mc68000 and the ad7245a is accom- plished using the circuit of figure 14. once again the ad7245a is used in the single buffered mode. a software routine for load- ing data to the ad7245a is given in table vi. in this example the ad7245a is located at address e000, and the 12-bit word is written to the dac in one move instruction. figure 14. ad7245a to 68000 interface table vl. sample routine for loading ad7245a from 68000 01000 move.w #x,d0 the desired dac data, x, is loaded into data re- gister 0. x may be any value between 0 and 4094 (decimal) or 0 and offf (hexadecimal). move.w d0,$e000 the data x is transferred between d0 and the dac latch. move.b #228,d7 control is returned to the system monitor program using these two trap #14 instructions. microprocessor interfacead7248a figure 15 shows the connection diagram for interfacing the ad7248a to both the 8085a and 8088 microprocessors. this scheme is also suited to the z80 microprocessor, but the z80 address/data bus does not have to be demultiplexed. data to be loaded to the ad7248a is right justified. the ad7248a is memory mapped with a separate memory address for the input latch high byte, the input latch low byte and the dac latch. data is first written to the ad7248a input latch in two write operations. either the high byte or the low byte data can be written first to the ad7248a input latch. a write to the ad7248a dac latch address transfers the input latch data to the dac latch and updates the output voltage. alternatively, the ldac input can be asynchronous or can be common to a number of ad7248as for simultaneous updating of a number of voltage channels. figure 15. ad7248a to 8085a/8088 interface a connection diagram for the interface between the ad7248a and 68008 microprocessor is shown in figure 16. once again the ad7248a acts as a memory mapped device and data is right justified. in this case the ad7248a is configured in the auto- matic transfer mode which means that the high byte of the input latch has the same address as the dac latch. data is written to the ad7248a by first writing data to the ad7248a low byte. writing data to the high byte of the input latch also transfers the input latch contents to the dac latch and updates the output.
ad7245a/ad7248a rev. a C14C figure 16. ad7248a to 68008 interface an interface circuit for connections to the 6502 or 6809 micro- processors is shown in figure 17. once again, the ad7248a is memory mapped and data is right justified. the procedure for writing data to the ad7248a is as outlined for the 8085a/8088. for the 6502 microprocessor the f 2 clock is used to generate the wr , while for the 6809 the e signal is used. figure 17. ad7248a to 6502/6809 interface figure 18 shows a connection diagram between the ad7248a and the 8051 microprocessor. the ad7248a is port mapped in this interface and is configured in the automatic transfer mode. data to be loaded to the input latch low byte is output to port 1. output line p3.0, which is connected to cslsb of the ad7248a, is pulsed to load data into the low byte of the input latch. pulsing the p3.1 line, after the high byte data has been set up on port 1, updates the output of the ad7248a. the wr in- put of the ad7248a can be hardwired low in this application because spurious address strobes on cslsb and csmsb do not occur. figure 18. ad7248a to mcs-51 interface
ad7245a/ad7248a rev. a C15C mechanical informationad7245a outline dimensions dimensions shown in inches and (mm). 24-pin plastic dip (n-24) 24-pin soic (r-24) package 28-terminal leadless ceramic chip carrier (e-28a) 24-pin cerdip (q-24) 28-terminal plastic leaded chip carrier (p-28a)
ad7245a/ad7248a rev. a C16C mechanical information ad7248a outline dimensions dimensions shown in inches and (mm). c1461C24C4/92 printed in u.s.a. 20-pin plastic dip (n-20) 20-pin cerdip (q-20) 20-lead soic (r-20) 20-terminal plastic leaded chip carrier (p-20a)

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